1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a copper structure, such as word lines, bit lines and interconnections with reduced erosion (dishing) and copper residue from chemical-mechanical polishing (CMP) by using a self-aligned copper deposition process.
2) Description of the Prior Art
Integrated circuits continue to increase in complexity each year. As applications develop for memories, microprocessors, and minicomputers there is an increasing demand for greater microminiturization, greater switching speeds, and smaller and less costly integrated circuit semiconductor devices.
Increased device microminiturization improves device performance and packing density while reducing cost per unit. However, microminiturization reduces yield and reliability, and degrades interconnect performance and noise margins.
Continued microminiturization of semiconductor devices using non-scaling aluminum lines would require the use of more metal layers, multi-level interconnections, and global planarization. The use of copper for interconnect and line metallurgy has long been considered as a possible alternative metallization material to aluminum and aluminum alloys due to its low resistivity and ability to reliably carry high current densities. However, its use has presented many manufacturing problems, such as the possibility of diffusion into the semiconductor substrate, the low adhesive strength of copper to various dielectric materials, and the difficulty in planarizing a copper layer without erosion or dishing occuring which reduces the performance and impedes the ability to stack multiple layers.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,011,580 (Pan et al.) discloses a copper plating process where a photoresist layer is used as a mask to form copper lines/interconnects during a rework process. However, this patent does not disclose or suggest planarizing the copper structures.
U.S. Pat. No. 5,242,861 (Inaba) and U.S. Pat. No. 5,071,518 (Pan) show methods for using photoresist as masks for electroplating copper lines.
U.S. Pat. No. 5,266,526 (Aoyama et al.) discloses a selective copper electroless plating process forming a copper interconnect in a trench.
U.S. Pat. No. 5,723,387 (Chen) and U.S. Pat. No. 5,821,168 (Jain) disclose dual damascene copper plating processes.
U.S. Pat. No. 5,766,492 (Sadahisa et al.) discloses a copper plating process for a printed circuit board using photoresist.